The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. Demands for new network applications and higher performance is requiring communication networks to operate at faster speeds (e.g., higher bandwidth). Many communication providers are using packet switching technology to achieve these goals. For example, using packet switching and routing technologies that support the Internet Protocol (IP).
Network processors have been used in packet switched networks for several years and provide cost-effective “high touch” packet services at moderate to high packet processing rates. The network processors often have specialized micro-engines used for packet processing applications. However, network processors are generally difficult to program and particularly difficult to program with new features. The processors also often experience performance cliffs when additional software features are enabled.
Network processor architectures also exist that provide multiple processors on a single chip. These multi-processor devices may include packet processing assists and specialized interfaces. These multi-processor architectures are usually general purpose devices that can be coded in the C programming language. However, the generality of these architectures tend to limit their scalability and throughput.
Some network processors are restricted to a non-ANSI subset of the C programming language. Due to the lack of a clean stack model, these processors cannot be considered general purpose.
Other network processor architectures use a pipeline of processors, and may also include special hardware assists for packet processing and for other inter-processor communications. However, pipeline processor systems are often asymmetric meaning not all processors have equal access to all resources.
Therefore, a need exists for a network processor with increased packet processing capability, scalability and operating flexibility. The present invention addresses this and other problems associated with the prior art.